In recent years, the need for realizing mass storage in nonvolatile semiconductor memory devices of such the type has made multi-valuing technologies standard, which allow one memory cell to have multiple threshold states to store multi-bit information (for example, Patent Document 1: JP 2001-93288A). Multi-valuing reduces the difference between threshold distributions for use in expression of data.
Therefore, due to factors such as failures in memory cells and applications of excessive write voltages, the threshold of a memory cell may be written erroneously in a different position from a desired position, thereby easily causing failed read.
In particular, failed read may often arise between adjacent threshold distributions. In order to correct the failed read to proper information, an external error correction circuit is introduced (for example, Patent Document 2: JP 2002-251884A). When a prior art method is used in bit assignment, however, the read number greatly differs between pages and according the error rate differs from page to page. Therefore, the error correction may not be executed with efficiency possibly.
In multi-valuing of the memory cell, a prior art read procedure (binary search reading method) causes such that the more the memory cell is multi-valued, the larger the total of read time becomes because the read time differs from each multi-bit page to other (Patent Document 1). Namely, a NAND flash memory requires time for providing data to external, other than reading operations. When the data output operation and the reading operation to the next page are executed in parallel and if the read time differs from page to page, the most read time-consuming page determines the read time because the data output time is constant. Therefore, it is required to balance the read time on pages.